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fixed bypass, latency ports in lv2

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This commit is contained in:
Stefano D'Angelo 2024-01-10 08:37:37 +01:00
parent 63c4cafd5e
commit a0b5d22fe0
1 changed files with 32 additions and 6 deletions
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38
templates/lv2/data/manifest.ttl
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@ -23,6 +23,37 @@
lv2:optionalFeature lv2:hardRTCapable ;
lv2:port [
{{~it.tibia.lv2.ports :p:i}}
{{?p.isBypass}}
a lv2:ControlPort ,
lv2:InputPort ;
lv2:designation lv2:enabled ;
lv2:name "Enabled" ;
lv2:shortName "Enabled" ;
lv2:symbol "{{=p.symbol}}" ;
lv2:default 1 ;
lv2:minimum 0 ;
lv2:maximum 1 ;
lv2:portProperty lv2:toggled ;
lv2:portProperty lv2:connectionOptional ;
lv2:portProperty lv2:integer ;
lv2:scalePoint [
rdfs:label "Off" ;
rdf:value 0
] , [
rdfs:label "On" ;
rdf:value 1
] ;
{{??p.isLatency}}
a lv2:ControlPort ,
lv2:OutputPort ;
lv2:designation lv2:latency ;
lv2:name "Latency" ;
lv2:shortName "Latency" ;
lv2:symbol "{{=p.symbol}}" ;
lv2:portProperty lv2:connectionOptional ;
lv2:portProperty lv2:integer ;
lv2:portProperty lv2:reportsLatency ;
{{??}}
a {{?p.type == "control"}}lv2:ControlPort{{??}}{{?p.cv}}lv2:CVPort{{??}}lv2:AudioPort{{?}}{{?}} ,
{{?p.direction == "input"}}lv2:InputPort{{??}}lv2:OutputPort{{?}} ;
lv2:name "{{=p.name}}" ;
@ -42,12 +73,6 @@
{{?p.sidechain}}
lv2:portProperty lv2:isSideChain ;
{{?}}
{{?p.isBypass}}
lv2:designation lv2:enabled ;
{{?}}
{{?p.isLatency}}
lv2:designation lv2:latency ;
{{?}}
{{?p.toggled}}
lv2:portProperty lv2:toggled ;
{{?}}
@ -74,6 +99,7 @@
{{?}}
{{?p.unit && p.unit in it.tibia.lv2.units}}
units:unit {{=it.tibia.lv2.ttlURI(it.tibia.lv2.units[p.unit])}} ;
{{?}}
{{?}}
lv2:index {{=i}}
{{?i < it.tibia.lv2.ports.length - 1}}